1. Field of the Invention
The present invention relates to signal bus interface circuits, and in particular, to signal bus interface circuits used for controlling access to signal buses including the initiation of wait states on such signal buses for selectively delaying such access.
2. Description of the Related Art
Complex digital logic systems typically use one or more signal buses for routing shared information such addresses and data. Connected to such signal buses are multiple blocks of logic circuits which, typically in a time shared manner, access such information via the signal buses. However, a problem which is becoming increasingly common as more sophisticated power management techniques are used is that of preventing movement of data into or out of logic blocks during transitions between power states, so as to prevent corruption of such data and/or risks of unauthorized access to sensitive data.
By way of example, a common power management technique involves the enabling and disabling of the clock signals to a block of logic for the purpose of minimizing its power consumption. Problems can arise, however, if such logic block is being accessed while its clock signal is in the process of being turned on or off. Such a problem can include corruption of data or, in the case of logic blocks involved in the storage or processing of sensitive data, a breach of security of such data. In other words, a security breach can occur if a logic block is being accessed while its clock is in the process of being turned off. This security breach can occur due to the unpredictability of results when access is being attempted during the disabling of the clock signal. Such a security breach can include the disclosure of sensitive data or placing the logic block in an unknown state.
Prior solutions to such problems have relied on software to not allow access by the system to those logic blocks that are being enabled or disabled. However, a shortcoming to this approach is that "no operation" (NOP) instructions must be inserted at the assembly language level to accomplish this. This adds to the code length, as well as to the time to develop the code, since pans of such code must be written at a low level. Additionally, in portable devices where memory space for code storage is limited, this extra code can add significantly to the expense of such devices.
Accordingly, it would be desirable to have a technique for preventing access to a logic block during such times its clock signal is being enabled or disabled, without needlessly adding to the length or complexity of the underlying software.